A PLL is a common component of several frequency synthesis systems. The PLL consists of a negative feedback circuit that allows multiplication of the frequency of a reference signal by a selected conversion factor; this results in the generation of a tuneable and stable output signal with the desired frequency.
For this purpose, a frequency divider scales the frequency of the output signal by the conversion factor. The resulting signal is fed back to a phase comparator, which detects a phase difference between the feedback signal and the reference signal; the phase comparator outputs a control current indicative of the phase difference. A loop filter integrates the control current into a corresponding voltage, which controls the frequency of the output signal accordingly. In a lock condition, the frequency of the feedback signal matches the frequency of the reference signal; therefore, the frequency of the output signal will be equal to the reference frequency multiplied by the conversion factor.
A particular architecture (commonly referred to as fractional-N) has become increasingly popular in the last few years, especially in wireless communication applications working at high frequency. In a fractional PLL, the dividing ratio of the frequency divider changes dynamically in the lock condition, so as to provide an average conversion factor equal to a fractional number. This structure allows finer resolution of the output frequency; moreover, the fractional PLL exhibits improved performance in terms of both settling time and phase noise.
Typically, the fractional PLL includes an accumulator that sums an adjusting value (defining a fractional part of the conversion factor) to itself continually. While the content of the accumulator is lower then its capacity (equal to the maximum allowed adjusting value), the frequency of the output signal is divided by an integer part of the conversion factor; whenever the accumulator overflows, the dividing ratio is incremented by one unit.
A problem of the fractional PLLs is that the feedback signal and the reference signal are not instantaneously at the same frequency in the lock condition. The periodicity of this phase error involves spurious signals (or spurs) at low-frequency offsets from a carrier. However, the content of the accumulator represents the current phase error between the feedback signal and the reference signal. Therefore, it is possible to reduce the level of the above-mentioned spurs with a technique also known as phase interpolation. For this purpose, the content of the accumulator is properly scaled and converted into a corresponding current; this current is then used to condition the control current that is injected into the loop filter, in order to have a control voltage always zero in the lock condition.
Operation of the accumulator can also be seen as a modulation of the adjusting value. In fact, the accumulator converts the fractional part of the conversion factor into a sequence of bits; the bits take the value 1 when the accumulator overflows or the value 0 otherwise. Therefore, it is possible to replace the accumulator (working as a first-order modulator) with an equivalent component.
For example, alternative architectures of the fractional PLL are based on a second or higher order sigma-delta modulator or on a multi-bit modulator. In both cases, the pattern of the dividing ratio is better shaped; particularly, the power of the spurs is pushed to higher frequency where the loop filter is more effective.
However, in the proposed architectures the value of the phase error (between the feedback signal and the reference signal) is not available in any accumulator. Therefore, it is not possible to condition the control current directly, in order to compensate the effects of the phase error caused by the modulation of the dividing ratio.